[Codel] hardware hacking on fq_codel in FPGA form at 10GigE

Jonathan Morton chromatix99 at gmail.com
Thu Dec 20 03:27:11 EST 2012

A small CPU can be made in perhaps 35K gates - something like an ARM7TDMI
or a Cortex-M0. It is common to stick one of those in a special purpose
chip to help with control logic.

But that would operate at a few hundred MHz, which leaves only a few cycles
per packet for small packets. That's not enough to run even a relatively
simple algorithm like codel.

Dedicated logic that *is* fast enough to run the algorithm on each packet
shouldn't be any bigger than such a CPU.

- Jonathan Morton
 On Dec 20, 2012 10:17 AM, "Hal Murray" <hmurray at megapathdsl.net> wrote:

> If I was going to do something like that, I'd build a small/simple CPU and
> do
> the work in microcode.
> > implementing {n,e,s}fq_codel onboard looks very feasible
> How many lines of assembler code would it take?
> How many registers do you need?  Do you need any memory other than queues?
> Maybe counters?
> > The only thing that is seriously serial about fq_codel is shooting the
> > biggest flow when the queue limit is exceeded, and that could be made
> > embarrassingly parallel with enough gates.There are no doubt other tricky
> > issues.
> Would it be better to do the fq work in the main CPU and let the FPGA grab
> packets from some shared  data structure in memory?  Can you work out a
> memory structure that doesn't need locks?
> --
> These are my opinions.  I hate spam.
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