[Codel] hardware hacking on fq_codel in FPGA form at 10GigE
hmurray at megapathdsl.net
Thu Dec 20 04:51:51 EST 2012
chromatix99 at gmail.com said:
> A small CPU can be made in perhaps 35K gates - something like an ARM7TDMI or
> a Cortex-M0. It is common to stick one of those in a special purpose chip to
> help with control logic.
I was thinking of a small/simple CPU with a wide instruction word to simplify
instruction decoding. We used to call it microcode rather than software.
My straw man would be an ALU that can add and compare and whatever else you
need, an instruction field for loading various hardware control registers and
another field for writing control registers, and other fields for
setting/testing flags and such. We used to put a next-instruction-address
field so there was no ALU for the PC. Branching was done by ORing bits into
> But that would operate at a few hundred MHz, which leaves only a few cycles
> per packet for small packets. That's not enough to run even a relatively
> simple algorithm like codel.
Sounds about right.
> Dedicated logic that *is* fast enough to run the algorithm on each packet
> shouldn't be any bigger than such a CPU.
You still need to describe the algorithm. That's going to be some sort of
FSM. How many steps (clock cycles) will that take?
I think the key idea behind what I was trying to say is that as soon as the
algorithm gets reasonably complicated, you probably want to think of it as
software rather than hardware.
The sort of microcode I'm thinking of should be a reasonable way to describe
that type of algorithm. If it can't come close to what raw hardware could do
then the design of the instruction set should be fixed.
These are my opinions. I hate spam.
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