[Make-wifi-fast] [Bloat] Van Jacobson's slides on timing wheels at netdevconf
swmike at swm.pp.se
Mon Jul 23 08:52:24 EDT 2018
On Sat, 21 Jul 2018, Jonathan Morton wrote:
> An example of such a situation would be sparse flows in DRR++, which is
> a key part of fq_codel and Cake. So to implement DRR++ using timing
> wheels, you have to choose your scheduling horizon carefully so as to
> minimise the delay to sparse packets.
At the spring IETF, there was talk from IEEE person about using ethernet
pause frames to get senders to stop talking for a while. My understanding
was that this was on microsecond scale or even nanosecond time scales.
One of the mentions in the presentation was on slide 10 about
"fat-buffered router". In the data center, these are kind of going away,
because on-die memory is small and rates are high. A 64x100GE forwarding
asic might have 16MB of buffer, which is very little buffer for the kind
of bit rates we're talking here.
https://www.youtube.com/watch?v=sJMvAqEQCBE 1h44m in (proposed IEEE
802.1Qcz work) is the one I am thinking of.
Wonder how this would interact with the timing wheel proposed by Van
Mikael Abrahamsson email: swmike at swm.pp.se
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