[Make-wifi-fast] Fwd: [NetFPGA-announce] Announcing NetFPGA PLUS 1.0

Dave Taht dave.taht at gmail.com
Wed Sep 29 12:21:54 EDT 2021

---------- Forwarded message ---------
From: Andrew Moore <andrew.moore at cl.cam.ac.uk>
Date: Fri, Sep 24, 2021 at 2:58 PM
Subject: [NetFPGA-announce] Announcing NetFPGA PLUS 1.0
To: <cl-netfpga-announce at lists.cam.ac.uk>

It is with great excitement we announce the release of NetFPGA PLUS.


NetFPGA PLUS 1.0 has arrived, available in a public repository to all,
links on the netfpga.org website. I’ve reprinted the outline, included
as part of the original announcement, at the bottom of this
newsletter. The overly optimistic timetable fell to the brutal
realities of the last 9 months.

NetFPGA PLUS has been  is a momentous effort that largely has fallen
to the broad shoulders of the increasingly slim NetFPGA team at
Cambridge; one person in particular deserves much credit for this huge
effort and for us achieving this first release.

On behalf of us all, I thank Yuta Tokusashi who has lead the NetFPGA
PLUS work throughout this effort and who has managed this despite the
extraordinary challenges of the last 18 months.

Many critical issues were managed and overcome with the expert
guidance of Noa Zilberman, while release testing and preparation would
not have been possible without the assistance of Salvator Galea.

This entire effort was enabled by many members of the excellent Xilinx
team from Gordon Brebner’s leadership and enthusiasm through to the
phenomenal efforts of the Open-NIC team; notably Yan Zhang, and Chris
Neely, as well as critical advice from Cathal McCabe, part of Xilinx
in Dublin.

My personal thanks and on behalf of the NetFPGA community to each of
them. (I’m excruciatingly aware the moment I send this email I will
realise I’ve not credited a critical member of the team - my apologies
in advance.)

I will leave some details to a future newsletter - in preparation -
but promise it shortly, as soon as we have all caught up on our sleep.

Do check out the new website, thanks to Adam Pettigrew for his efforts
there; and of course do check out the public, openly available, Apache
licensed, NetFPGA PLUS codebase too!

Items planned for the next announcement will include

1. License change for NetFPGA
2. NetFPGA PLUS plans
3. NetFPGA SUME status

Thank you all,
Andrew Moore
on behalf of the NetFPGA team.

[direct copy of the PLUS announcement from the December 2020 NetFPGA newsletter]

5. Announcing NetFPGA PLUS (formerly NetFPGA 2020) - 100Gbps and beyond.

At the ACM SOSR19 keynote, I announced the NetFPGA 2020 project,
taking forward the NetFPGA ecosystem to 100Gbps.

Called NetFPGA PLUS, this work does not require a bespoke NetFPGA
board. Instead the codebase is designed to work across a number of the
(commodity) Alveo boards that utilise the Xilinx UltraScale+ FPGA
family. This project will provide more options for the NetFPGA
community and more opportunities for NetFPGA work to continue to be
the foundation stone of future education, future designs, future
research, and ongoing success.

At this time, we have been testing across a subset of the Xilinx Alveo
board family: U200, U250, U280, and also the ancestor VCU1525 board.

A typical specification (VCU1525/U200 in this case) is support for two
QSFP28 100G ports, PCIe Gen3 x16 or Gen4 x8, up to 64GB of DDR4, and
an FPGA which sports 2,586K system logic cells, 345Mbit of on chip
memory and a great many other features beside. The U250 and U280 are
even higher specification systems.

Built upon the Xilinx Vivado toolchain, the initial release of the
NetFPGA-PLUS system still provides the same nf_datapath architecture
that we know and love.  The hybrid approach of using NetFPGA and
Xilinx components brings standard interfaces and board-specific blocks
(e.g., CMAC, PCIe), holds promise of an easier migration between
platforms, while holding constant the NetFPGA datapath and networking
capabilities, alongside host software and the build, test and
simulation infrastructure critical for development.

In the first instance we are focussed upon those users with one or
more Alveo boards in hand (or accessible remotely). The initial
release (due early in the new year) will have the basic reference
designs of NetFPGA-SUME:
-  Network Interface Card reference project
-  Switch reference project (simple switch and learning switch), and
-  IPv4 Router reference project

along with the standard NetFPGA Python3 based simulation and hardware
testing framework.

Also on the planning list (a release for Q3 2021):
- Fully integrated P4 compilation support, to provide an open P4
hardware platform
- MAC/PHY support for QSFP28 to 4xSFP28, permitting up to 8 10/25Gbps ports
- New generation open source network tester capable of many 100Gbps.

cl-netfpga-announce mailing list
cl-netfpga-announce at lists.cam.ac.uk

Fixing Starlink's Latencies: https://www.youtube.com/watch?v=c9gLo6Xrwgw

Dave Täht CEO, TekLibre, LLC

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