From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.bufferbloat.net (Postfix) with ESMTPS id E3A7A3CB37 for ; Tue, 6 Sep 2022 18:42:10 -0400 (EDT) Received: by mail-wm1-x331.google.com with SMTP id c131-20020a1c3589000000b003a84b160addso9842843wma.2 for ; Tue, 06 Sep 2022 15:42:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=VZCRnwVh5A4M19XD3R/8cn4rOHEK6FznPj7uO3wCOu4=; b=F15IFjITnv44A66mwEm8o441UhZPFTQocnzZ3WgPVzBH6pkDRBscERnH4dBsNaJBKw i5T91j+zarlcu7XS/HDtqjhXy5dgeqd5GHXWFG9jL8/9x7JLhBDfnTwTosXBoAh5eupR uWpLgTjssoQukGLZ4sLPtJdoYLHiaCATIXYD0JfW0iARChOmkrcNkdaJDaCUuaJyGfXX 36cR9Zdqb8ICOwnwcYY8uaRTsUE7Zcy5kk530pZG5axwJZykufQoGTextS2gq/iNrKD5 MTjtrIG3lNJJoaQ1tXbJ4P4YNRQUgsjCseBZw9p2ORFFxDQB3vcDLTYSMoyyDZHgXcDr NVCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=VZCRnwVh5A4M19XD3R/8cn4rOHEK6FznPj7uO3wCOu4=; b=m/TOkJjB59FY4j/l3mn5ekQSXZgwdRB/60mcTKBjX1ppVfQQT6ZZOcbgMIP59ZWqrv hDi6v70NtmY7kPho7vc5GRpVh3ZflsqeeaFIhOc/RNga5XeH3mdf2onKoc3KnJ+Y0LHb OgG3IGmlNLsqTZE85DU4GIiVcamDC0S1xWppoT5pz+haCJ0IsJd6I+D88mCRqG4Y2PAB Alze3B4/rW+k4xb1QXg/5S7zpmRmFAVHpt62UVpxro2pEja3ASLhGVnBvH6TBCs2yBOA MWBJK52fmHBEEJObBKI1nVzINej/SOLsqC8ZBhhncx4DrDrlhNDGAs2N1H+awajAXQrm g+qw== X-Gm-Message-State: ACgBeo1eoVlZ3Z6WX7nHhw+rXyNEG056QlwaGIUBm9B8t5rJdXKkD/SD IpOchfaIW01pHNfOf6u2i74lxwP9OKV0qhxmfh/AtA== X-Google-Smtp-Source: AA6agR42u5R+EIoeh2RA99ygm7HAv5xZYjs6QFVtuibCn4eTRS/lr54CE6l7M+KEi16P5T4SpfpqzqVvgsGQAq4uxdg= X-Received: by 2002:a05:600c:2c47:b0:3a6:4623:4ccf with SMTP id r7-20020a05600c2c4700b003a646234ccfmr316935wmg.85.1662504129702; Tue, 06 Sep 2022 15:42:09 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Vint Cerf Date: Tue, 6 Sep 2022 18:41:58 -0400 Message-ID: To: Bruce Perens Cc: Dave Taht , Dave Taht via Starlink Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="0000000000001c852305e809e863" Subject: Re: [Starlink] risc-v in space X-BeenThere: starlink@lists.bufferbloat.net X-Mailman-Version: 2.1.20 Precedence: list List-Id: "Starlink has bufferbloat. Bad." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Sep 2022 22:42:11 -0000 --0000000000001c852305e809e863 Content-Type: multipart/alternative; boundary="000000000000170ab905e809e8d3" --000000000000170ab905e809e8d3 Content-Type: text/plain; charset="UTF-8" ok to share with non-list colleagues? v On Tue, Sep 6, 2022 at 3:51 PM Bruce Perens via Starlink < starlink@lists.bufferbloat.net> wrote: > > >> The larger question I have though, is how much do we know now about >> rad-hardening electronics in space? >> > I've learned some. > > Not quite related to that, but if you want to run an Open Source Space > project in the US without running afoul of ITAR and EAR, I can tell you > how. The policy I created was approved by Department of State and > Department of Commerce. > > Here is a simple explanation for the uninitiated: > > This is less severe for LEO because the satellites don't traverse the van > Allen belts. But the coronal mass ejections we are having just now and > their associated electrical effects could make the situation worse whatever > orbit you are in. > > The largest problem we have is that radiation can trigger a junction to > conduct. If you have built your chip on a semiconductor substrate, that > means that some random chip feature can start conducting to the substrate > and latch that way until power is removed. Overcurrent can blow details > right off of the chip. So, you must build your chip on an insulating > substrate. This used to be silicon on sapphire, which was incredibly > expensive. Silicon on insulator does the job. It happens that many common > FPGAs are built on insulator, so that is a cheap way to get space-robust > processing. > > Second issue is that you can get random triggering of junctions. This > means that chips can do the unexpected, and you need redundancy on-chip or > off, and a way to power off the chip because sometimes nothing else will > reset it. You also need error-correction on your memory, and a process that > continually "washes" your memory by reading it, and writing the corrected > data. > > It doesn't work to shield your electronics with some dense material like > lead. The problem is that a high-energy particle can hit that and turn into > lots of lower-energy particles that are actually more harmful. So, a thick > enough shield to stop all of these secondary emissions is usually not > practical. > > If you have enough money, you can pay a company like Vorago for a > space-qualified processor. It's pin-compatible with a non-space version of > the same CPU, so you can test it cheaply. > > and of course we see astronauts using COTS laptops. > > > Those laptops aren't mission-critical. The risk to the astronauts is > probably a worse problem, for missions that traverse the van Allen belts. > Apollo used the location of a low-energy region, and got through there > quickly. Interplanetary missions are probably going to require lots of > water around the place where the people stay when there's a solar flare. > > Thanks > > Bruce > > > _______________________________________________ > Starlink mailing list > Starlink@lists.bufferbloat.net > https://lists.bufferbloat.net/listinfo/starlink > -- Please send any postal/overnight deliveries to: Vint Cerf Google, LLC 1900 Reston Metro Plaza, 16th Floor Reston, VA 20190 +1 (571) 213 1346 until further notice --000000000000170ab905e809e8d3 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
ok to share with non-list colleagues?

v=


On Tue, Sep 6, 2022 at 3:51 PM Bruce Perens via Starli= nk <starlink@lists.buf= ferbloat.net> wrote:


The larger question I have though, is how much do we know now about rad-har= dening electronics in space?
I've learned some.

Not quite related to that, but if you want to run an= Open Source Space project in the US without running afoul of ITAR and EAR,= I can tell you how. The policy I created was approved by Department of Sta= te and Department of Commerce.

Here is a simple ex= planation for the uninitiated:

This is less severe= for LEO because the satellites don't traverse the van Allen belts. But= the coronal mass ejections we are having just now and their associated ele= ctrical effects could make the situation worse whatever orbit you are in.

The largest problem we have is that radiation can t= rigger a junction to conduct. If you have built your chip on a semiconducto= r substrate, that means that some random chip feature can start conducting = to the substrate and latch that way until power is removed. Overcurrent can= blow details right off of the chip. So, you must build your chip on an ins= ulating substrate. This used to be silicon on sapphire, which was incredibl= y expensive. Silicon on insulator does the job. It happens that many common= FPGAs are built on insulator, so that is a cheap way to get space-robust p= rocessing.

Second issue is that you can get random= triggering of junctions. This means that chips can do the unexpected, and = you need redundancy on-chip or off, and a way to power off the chip because= sometimes nothing else will reset it. You also need error-correction on yo= ur memory, and a process that continually "washes" your memory by= reading it, and writing the corrected data.

It do= esn't work to shield your electronics with some dense material like lea= d. The problem is that a high-energy particle can hit that and turn into lo= ts of lower-energy particles that are actually more harmful. So, a=C2=A0thi= ck enough shield to stop all of these secondary emissions is usually not pr= actical.

If you have enough money, you can pay a c= ompany like Vorago for a space-qualified processor. It's pin-compatible= with a non-space version of the same CPU, so you can test it cheaply.

and of course we see astronauts using COTS laptops.

Those laptops aren't mission-critical. The risk to the astrona= uts is probably a worse problem,=C2=A0for missions that traverse the van Al= len belts. Apollo used the location of a low-energy region, and got through= there quickly. Interplanetary missions are probably going to require lots = of water around the place where the people stay when there's a solar fl= are.

=C2=A0 =C2=A0 Thanks

=C2=A0 =C2=A0 Bruce


_______________________________________________
Starlink mailing list
Starlin= k@lists.bufferbloat.net
https://lists.bufferbloat.net/listinfo/starlink


--
Please send any postal/ove= rnight deliveries to:
Vint Cerf
Google, LLC
<= div>1900 Reston Metro Plaza, 16th Floor
Reston, VA 20190
+1 (571) 213 1346

<= /div>

until further notice


=

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