From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oa1-x2a.google.com (mail-oa1-x2a.google.com [IPv6:2001:4860:4864:20::2a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.bufferbloat.net (Postfix) with ESMTPS id 65AC63CB37 for ; Tue, 6 Sep 2022 15:51:37 -0400 (EDT) Received: by mail-oa1-x2a.google.com with SMTP id 586e51a60fabf-1278a61bd57so12301824fac.7 for ; Tue, 06 Sep 2022 12:51:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=perens.com; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=HFjUr7vFB0hXjar8hgqcKsNz0yNd1bSZo3uN87C7/Yo=; b=vpM7E+3Ywd2IJyAww48vMAluPMB6JpfjspH19gVLSat7QwZaZvzlOaQGtlI+8ySNNM yOl+y8Gl5N3FOdLafm8uYNgMdQl7gTYeAG3uu7RrU3XG4+c/V2F/kdpE3HXAncomMMR0 YzMwcT6urXFvBA9vNCDk2lSZg/8E86OoMB9Q4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=HFjUr7vFB0hXjar8hgqcKsNz0yNd1bSZo3uN87C7/Yo=; b=qfJN5z02MaQfuvzOj9zX2+qHFI3nvHHk05yatgAKj/zQcQi21QzM5PmqlLt+R8qXtW PTIbMj4h7sNzDYDE9nykv3K9tLfxZDzL7vIJgEllE5Ikyj/fUSxiNee1bb9oMIlRmdDG im7DWq1ONVK7Q6XbPRdh+PkYZjQRi+74U517Zu+ncr9vrFJDntctlny7+rH498ctdu5c bZ3sJej/JMxXmWs6UyyTJf8zWXRJq4tiitivZyW/qzB/qOzBion1mtC6qy9LOsk+Q3Px dC7OqthEVNw1QbASrfmci4Dnk4Q9dsGmUjTpImOWlvhqRAaI2DJjY0CzZBKi5/+IUrx2 iIYQ== X-Gm-Message-State: ACgBeo00EE8iQTthDbm44GH2EGBVL+uUIj5GF1gWRSJnsGjr4cKkWqQo P8CK3wlAZAxTts29OsnSjv3n8fjaT5PszBnX4OLVrjiLQrIwpA== X-Google-Smtp-Source: AA6agR4QF2fPhuLb5rIj4YgjvNcLxDQ2kWnnMI1nywrS6TZ9m0zooFUCHgEf6kT54Ih2B+SBfzDrhyqrrA906Eq87o0= X-Received: by 2002:a05:6808:3010:b0:337:b782:842a with SMTP id ay16-20020a056808301000b00337b782842amr10580436oib.117.1662493896444; Tue, 06 Sep 2022 12:51:36 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Bruce Perens Date: Tue, 6 Sep 2022 12:51:25 -0700 Message-ID: To: Dave Taht Cc: Dave Taht via Starlink Content-Type: multipart/alternative; boundary="00000000000023a1e705e807862d" Subject: Re: [Starlink] risc-v in space X-BeenThere: starlink@lists.bufferbloat.net X-Mailman-Version: 2.1.20 Precedence: list List-Id: "Starlink has bufferbloat. Bad." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Sep 2022 19:51:37 -0000 --00000000000023a1e705e807862d Content-Type: text/plain; charset="UTF-8" > > The larger question I have though, is how much do we know now about > rad-hardening electronics in space? > I've learned some. Not quite related to that, but if you want to run an Open Source Space project in the US without running afoul of ITAR and EAR, I can tell you how. The policy I created was approved by Department of State and Department of Commerce. Here is a simple explanation for the uninitiated: This is less severe for LEO because the satellites don't traverse the van Allen belts. But the coronal mass ejections we are having just now and their associated electrical effects could make the situation worse whatever orbit you are in. The largest problem we have is that radiation can trigger a junction to conduct. If you have built your chip on a semiconductor substrate, that means that some random chip feature can start conducting to the substrate and latch that way until power is removed. Overcurrent can blow details right off of the chip. So, you must build your chip on an insulating substrate. This used to be silicon on sapphire, which was incredibly expensive. Silicon on insulator does the job. It happens that many common FPGAs are built on insulator, so that is a cheap way to get space-robust processing. Second issue is that you can get random triggering of junctions. This means that chips can do the unexpected, and you need redundancy on-chip or off, and a way to power off the chip because sometimes nothing else will reset it. You also need error-correction on your memory, and a process that continually "washes" your memory by reading it, and writing the corrected data. It doesn't work to shield your electronics with some dense material like lead. The problem is that a high-energy particle can hit that and turn into lots of lower-energy particles that are actually more harmful. So, a thick enough shield to stop all of these secondary emissions is usually not practical. If you have enough money, you can pay a company like Vorago for a space-qualified processor. It's pin-compatible with a non-space version of the same CPU, so you can test it cheaply. and of course we see astronauts using COTS laptops. Those laptops aren't mission-critical. The risk to the astronauts is probably a worse problem, for missions that traverse the van Allen belts. Apollo used the location of a low-energy region, and got through there quickly. Interplanetary missions are probably going to require lots of water around the place where the people stay when there's a solar flare. Thanks Bruce --00000000000023a1e705e807862d Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


The larger question I have though, is how much do we know now about rad-har= dening electronics in space?
I've learned some.

Not quite related to that, but if you want to run an= Open Source Space project in the US without running afoul of ITAR and EAR,= I can tell you how. The policy I created was approved by Department of Sta= te and Department of Commerce.

Here is a simple ex= planation for the uninitiated:

This is less severe= for LEO because the satellites don't traverse the van Allen belts. But= the coronal mass ejections we are having just now and their associated ele= ctrical effects could make the situation worse whatever orbit you are in.

The largest problem we have is that radiation can t= rigger a junction to conduct. If you have built your chip on a semiconducto= r substrate, that means that some random chip feature can start conducting = to the substrate and latch that way until power is removed. Overcurrent can= blow details right off of the chip. So, you must build your chip on an ins= ulating substrate. This used to be silicon on sapphire, which was incredibl= y expensive. Silicon on insulator does the job. It happens that many common= FPGAs are built on insulator, so that is a cheap way to get space-robust p= rocessing.

Second issue is that you can get random= triggering of junctions. This means that chips can do the unexpected, and = you need redundancy on-chip or off, and a way to power off the chip because= sometimes nothing else will reset it. You also need error-correction on yo= ur memory, and a process that continually "washes" your memory by= reading it, and writing the corrected data.

It do= esn't work to shield your electronics with some dense material like lea= d. The problem is that a high-energy particle can hit that and turn into lo= ts of lower-energy particles that are actually more harmful. So, a=C2=A0thi= ck enough shield to stop all of these secondary emissions is usually not pr= actical.

If you have enough money, you can pay a c= ompany like Vorago for a space-qualified processor. It's pin-compatible= with a non-space version of the same CPU, so you can test it cheaply.

and of course we see astronauts using COTS laptops.

Those laptops aren't mission-critical. The risk to the astrona= uts is probably a worse problem,=C2=A0for missions that traverse the van Al= len belts. Apollo used the location of a low-energy region, and got through= there quickly. Interplanetary missions are probably going to require lots = of water around the place where the people stay when there's a solar fl= are.

=C2=A0 =C2=A0 Thanks

=C2=A0 =C2=A0 Bruce


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