[Cake] cake target corner cases?

[Sebastian Moeller]

Dear cake committee,

I just played around with the most recent sch_cake and noticed:

user at computer:~/CODE/tc-adv/tc> sudo tc-adv qdisc del dev eth0 root
user at computer:~/CODE/tc-adv/tc> sudo tc-adv qdisc replace dev eth0 root cake bandwidth 1Mbit ; sudo tc-adv -s qdisc
qdisc cake 8005: dev eth0 root refcnt 6 bandwidth 1Mbit diffserv4 flows rtt 100.0ms raw 
 Sent 0 bytes 0 pkt (dropped 0, overlimits 0 requeues 0) 
 backlog 0b 0p requeues 0 
capacity estimate: 1Mbit
             Tin 0       Tin 1       Tin 2       Tin 3  
  thresh       1Mbit   937504bit     750Kbit     250Kbit
  target      18.2ms      19.4ms      24.2ms      72.7ms
interval     145.3ms     155.0ms     193.8ms     581.4ms
Pk-delay         0us         0us         0us         0us
Av-delay         0us         0us         0us         0us
Sp-delay         0us         0us         0us         0us
  pkts             0           0           0           0
  bytes            0           0           0           0
way-inds           0           0           0           0
way-miss           0           0           0           0
way-cols           0           0           0           0
  drops            0           0           0           0
  marks            0           0           0           0
Sp-flows           0           0           0           0
Bk-flows           0           0           0           0
last-len           0           0           0           0
max-len            0           0           0           0

Here target is always 12.5% of interval instead of the expected 6.25%
1/16 = 0.0625
72.7/581.4 = 0.125042999656
24.2/193.8 = 0.124871001032
19.4/155.0 = 0.125161290323
18.2/145.3 = 0.125258086717
But the bandwidth is really low, so pushing target closer to the bandwidth conserving side of the codel rationale might be fine, since latency is bad to begin with and bandwidth also pretty scarce. But it might be interesting to do a few more measurements at low bandwidths to confirm that the 12.5% of interval logic holds water; one could also argue that people with such links (a lot of DSL lines have even less upload, so this certainly is not extreme) might think that any added ms of delay matters (more than bandwidth); currently we leave the user no remedy...





user at computer:~/CODE/tc-adv/tc> sudo tc-adv qdisc del dev eth0 root
user at computer:~/CODE/tc-adv/tc> sudo tc-adv qdisc replace dev eth0 root cake bandwidth 10Mbit ; sudo tc-adv -s qdisc
qdisc cake 8006: dev eth0 root refcnt 6 bandwidth 10Mbit diffserv4 flows rtt 100.0ms raw 
 Sent 0 bytes 0 pkt (dropped 0, overlimits 0 requeues 0) 
 backlog 0b 0p requeues 0 
capacity estimate: 10Mbit
             Tin 0       Tin 1       Tin 2       Tin 3  
  thresh      10Mbit    9375Kbit    7500Kbit    2500Kbit
  target       6.2ms       6.2ms       6.2ms       7.3ms
interval     100.0ms     100.0ms     100.0ms     101.0ms
Pk-delay         0us         0us         0us         0us
Av-delay         0us         0us         0us         0us
Sp-delay         0us         0us         0us         0us
  pkts             0           0           0           0
  bytes            0           0           0           0
way-inds           0           0           0           0
way-miss           0           0           0           0
way-cols           0           0           0           0
  drops            0           0           0           0
  marks            0           0           0           0
Sp-flows           0           0           0           0
Bk-flows           0           0           0           0
last-len           0           0           0           0
max-len            0           0           0           0

This looks okay, except Tin3 has target at 7.3/101.0 = 0.0722772277228 7% of interval.



Both observations might actually be on purpose, but if so we should document that behavior as expected, for example in the man page…

Best Regards
	Sebastian