[Cake] Configuring cake for VDSL2 bridged connection
alan.christopher.jenkins at gmail.com
Wed Aug 24 15:49:42 EDT 2016
On 24/08/16 20:47, Alan Jenkins wrote:
> So you can read off (+calculate) overall throughput, in both directions.
> And it looks like your latency under load rises by only about 2ms.
> That's the sort of thing we're aiming for.
> Pure codel aims for 5ms, so I take it you're using fq_codel.
/reads subject line
or using standard cake, and not passing `flowblind` to disable the fair
> And... yes
> (1500 * 8) / 4_000_000 = 0.003
> It takes 3ms to transmit a full packet in the slower direction. So
> when it's busy, ping can be delayed on average by 1.5ms (while the
> current packet is transmitted). Something like that anyway.
> On 24/08/16 20:33, techicist at gmail.com wrote:
>> Thanks for the reply. I understand now 😀
>> What can be taken from these graphs? I'm afraid I really am lost now.
>> Cake mailing list
>> Cake at lists.bufferbloat.net
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