[Cake] [LEDE-DEV] Cake SQM killing my DIR-860L - was: [17.01] Kernel: bump to 4.4.51
chromatix99 at gmail.com
Mon Mar 6 13:46:06 EST 2017
> On 6 Mar, 2017, at 20:08, Benjamin Cronce <bcronce at gmail.com> wrote:
> Depends on how short of a timescale you're talking about. Shared global state that is being read and written to very quickly by multiple threads is bad enough for a single package system, but when you start getting to something like an AMD Ryzen or NUMA, shared global state becomes really expensive. Accuracy is expensive. Loosen the accuracy and gain scalability.
I’m talking about timer event latency timescales, so approx 1ms on Linux. The deficit-mode shaper automatically and naturally adapts to whatever timer latency is actually experienced. A token-bucket shaper has to be configured in advance with a burst size, which it uses whether or not it is warranted to do so.
The effects are measurable on single TCP flows at 20Mbps (so slightly more than 1Kpps peak), as they modify Codel’s behaviour. Cake achieves higher average throughput than HTB+fq_codel with its more accurate shaping, because Codel isn’t forced into overcorrecting after accepting several sub-bucket bursts in sequence.
Anyway, these are concerns I would want to go away and think about for a while, before committing to a design. That’s precisely why I don’t have mental bandwidth for it right now.
- Jonathan Morton
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