dave.taht at gmail.com
Wed Aug 1 16:06:14 EDT 2018
On Wed, Aug 1, 2018 at 5:49 AM dpreed at deepplum.com <dpreed at deepplum.com> wrote:
> Yeah. Small FF 2 port Celeron board is what I use. And I have a 4 port Atom that runs like a bat out of hell.
> Currenty fiddling with Xilinx Dev boards, just put packet processing in FPGA for Cake, and no problem with 2.5 - 10 Gb/sec. Just need a free piece of low level SFP+ interfacing logic.
cool. which? ultrascale?
I was looking over
> My use case is using the open ChipLink/TileLink bus from RISCV rather than PCIe, making something that might be an open source ASIC design.
How fast can that cpu context switch?
> -----Original Message-----
> From: "Toke HÃ¸iland-JÃ¸rgensen" <toke at toke.dk>
> Sent: Wed, Aug 1, 2018 at 5:23 am
> To: "Dave Taht" <dave.taht at gmail.com>, "Daniel Ezell" <dezell at stonescry.com>
> Cc: "Dave Taht" <dave.taht at gmail.com>, "Daniel Ezell" <dezell at stonescry.com>, "Cake List" <cake at lists.bufferbloat.net>, cerowrt-devel at lists.bufferbloat.net
> Subject: Re: [Cerowrt-devel] expressobin
> Dave Taht writes:
> > It turns out it's just two ethernets with one, connected to a 2 port
> > switch. Not what I wanted. I'd wanted something different from the
> > apu2 or edgerouter X to play with, and I know the mvneta driver was
> > bql'd.
> I bought one of these to play with:
> x86 (i3 processor), four real ethernet ports, and passively cooled. A
> bit pricy, though; more than $400... But doubles well as a combined
> switch and media player :)
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