[Codel] [Cerowrt-devel] hardware hacking on fq_codel in FPGA form at 10GigE
dwmw2 at infradead.org
Fri Dec 21 17:08:23 EST 2012
On Fri, 2012-12-21 at 22:56 +0100, John Crispin wrote:
> > So the ATM driver would have to go out of its way to screw you over¹.
> the lantiq atm/dsl drivers use a dma ring to push packets from the atm
> layer to the dsl modem core. this ring needs to be 2 packets big as a
> minimum to have the hardware work. however, using software we can make
> sure that only 1 packet at a tim eis inside the ring. this is what my
> current dirty hack does.
You shouldn't need that hack any more. With the current core ATM code
you should only have two packets in the queue anyway — the one the
hardware is *currently* working on, and the next one ready to be sent
(which is necessary to avoid introducing too much latency between
packets. Your ADSL uplink is *very* limited, and you really want to be
sure you're using it *all*).
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